The present embodiments relate to data converters, and are more particularly directed to converters using resistor strings.
Data converters may be used in various types of electronic circuits, or may be formed as a single integrated circuit device. Such converters typically take one of two forms, either as a digital-to-analog converter ("DAC") or an analog-to-digital converter ("ADC"). For the DAC, its operation converts an input digital signal to an output analog signal, typically where the amplitude of the output analog signal corresponds directly to the magnitude of the input digital signal. Conversely, the ADC converts an input analog signal to an output digital signal, typically where the value of the output digital signal corresponds directly to the amplitude of the input analog signal. In many configurations, both DACs and ADCs implement a resistor string that includes a number of series-connected resistors, where each resistor provides a voltage tap at each of its ends. Typically, the overall string is biased at opposing ends by two different reference voltages, where for example one such voltage is a positive voltage and the other is ground. Also in this regard, in an effort to maintain the linearity between the digital input and the analog output, a common concern in the art is to endeavor to ensure that each resistor in the string has as dose to the same resistance value as all other resistors in the string. Accordingly, the resistor string forms a series voltage dividing network and each of the voltage taps is accessible as part of the operation for the data conversion (i.e., either from digital to analog, or analog to digital).
For further background to converters and by way of example, FIG. 1 illustrates a typical configuration of a prior art DAC 10, and is detailed briefly below. In addition, since the primary focus of the preferred embodiments described later is directed to resistor strings as used in either a DAC or an ADC, the following discussion provides one example of such a string as used in a DAC, but is not unduly lengthened by also providing a detailed analysis of an ADC. Instead, such an understanding is left to one skilled in the art.
FIG. 1 illustrates a typical configuration of a prior art DAC 10, and is detailed briefly here with additional detail ascertainable by one skilled in the art. By way of example and as appreciated later, DAC 10 is a 4-input 16-output DAC, while numerous other dimensions may exist for different DAC configurations. In general and as detailed below, DAC 10 is operable to receive a 4-bit input word, designated from least significant bit to most significant bit as I.sub.0 -I.sub.3, and in response to the magnitude of that input to output a corresponding analog voltage. Before detailing this operation, it is first instructive to examine the devices and connections of DAC 10. In this regard, DAC 10 includes a series-connected resistor string designated generally at 12, and which forms a meander in that it serpentines back and forth. Additionally, DAC 10 is generally an array in nature, having a number of bit lines in the vertical dimension and a number of word lines in the horizontal dimension. Since the example of DAC 10 presents a 4-input 16-output DAC, the array of DAC 10 includes four bit lines BL0 through BL3, and four word lines WL0 through WL3. Also for the current example of a 4-to-16 DAC, resistor string 12 includes fifteen resistive elements R0 through R14. Resistive elements R0 through R14 may be formed using various techniques, where the particular technique is not critical to the present inventive teachings. Regardless of the technique used to form the resistive elements, ideally each resistive element has as close to the same resistance value as all other resistors in the string. Moreover, a voltage source V.sub.REF1 is applied across resistor string 12, and may be of any suitable biasing voltage, which for current applications is typically on the order of 2.0 volts. For DAC 10, string 12 is biased between V.sub.REF1 and ground, but it should be understood that in other configurations two different non-ground potentials may be connected at opposing ends of string 12, while a key notion for purposes of the present teachings is the difference between these potentials. Thus, where ground is connected to one end of the string, it is easily appreciated that this difference of the potentials at the ends of the string equals V.sub.REF1. In any event, and for reasons detailed below, note that V.sub.REF1 is typically far less than the V.sub.S1, the supply voltage for the remaining circuitry in DAC 10, in order to provide an adequate voltage difference between the two. Indeed, in the current example, this difference equals three volts (i.e., V.sub.S1 -V.sub.REF1 =5.0-2.0=3.0 volts).
Looking to the detailed connections with respect to the resistive elements in string 12, each resistive element provides two taps from which a voltage may be measured as detailed below. For example, looking to resistive element R0, it provides a tap T0 and a tap T1, while resistive element R1 shares the same tap T1 and provides another tap T2, and so forth. Each tap has a switching device connected between it and a corresponding output bit line. In the current example, each of these switching devices is an n-channel field effect transistor, and is labeled for convenience by combining the abbreviation ST (i.e., switching transistor) with the same numeric identifier corresponding to the tap to which a source/drain of the transistor is connected. For example, a source/drain of transistor ST0 is connected to tap T0, a source/drain of transistor ST1 is connected to tap T1, and so forth. Further, the switching transistors are arranged so that a like number of taps are coupled via corresponding switching transistors to a corresponding one of the bit lines. In the current example of DAC 10, four taps are coupled in this manner to a corresponding bit line. For example, taps T0 through T3 are coupled, via corresponding switching transistors ST0 through ST3, to bit line BL0. As another example, taps T4 through T7 are coupled, via corresponding switching transistors ST4 through ST7, to bit line BL1. Each bit line BL0 through BL3 is coupled via a respective column access transistor, CAT0 through CAT3, to a column decoder 14. More particularly and for reasons evident below, column decoder 14 is coupled to receive the two most significant bits (MSBs) of the 4-bit word input to DAC 10, and in response column decoder 14 controls the gates of column access transistors CAT0 through CAT3. Lastly, it should be understood that column decoder 14 operates in response to an overall system supply voltage V.sub.S1 which, as discussed further below, is typically on the order of five volts.
Retuning now to switching transistors ST0 through ST15, and given the array nature of DAC 10, it is further appreciated that the switching transistors are arranged so that a like number of switching transistors are controlled, via connection to their gates, by a corresponding word line which is further connected to row decoder 16. Like column decoder 14, row decoder 16 is also responsive to the system supply voltage V.sub.S1. Returning to the connectivity between row decoder 16 and the switching transistors, and in the current example of DAC 10, the gates of four switching transistors are coupled to each corresponding word line. For example, the gates of switching transistors ST0, ST7, ST8, and ST15 are coupled to word line WL0. As another example, the gates of switching transistors ST1, ST6, ST9, and ST14 are coupled to word line WL1. Lastly in this regard, and for reasons evident below, row decoder 16 is coupled to receive the two least significant bits (LSBs) of the 4-bit word input to DAC 10 (i.e., bits I.sub.1 and I.sub.0), and is also controlled in response to the least significant bit ("Isb"), I.sub.2, of the two MSBs input to column decoder 14. More particularly, each least significant bit I.sub.0 and I.sub.1 is coupled as an input to a corresponding exclusive OR gate EOG0 and EOG1 as a first input, while the second input of exclusive OR gates EOG0 and EOG1 is connected to receive 12 (i.e., the least significant bit of the two MSBs input to column decoder 14). In response to these bits, row decoder 16 controls the gates of switching transistors ST0 through ST15 as detailed below.
The operation of DAC 10 is now described, first in general and then more specifically through the use of a few examples. A 4-bit digital word is connected to inputs I.sub.0 through I.sub.3 and ultimately causes signals to pass to column decoder 14 and row decoder 16. Generally, row decoder 16 includes sufficient logic circuitry or the like to respond by asserting one of word lines WL0 through WL3, thereby providing an enabling voltage to the gates of the four switching transistors coupled to the asserted word line. Similarly, column decoder 14 includes sufficient logic circuitry or the like to respond by enabling one of column access transistors CAT0 through CAT3, thereby causing the enabled transistor to pass the voltage from the corresponding one of bit lines BL0 through BL3 to output V.sub.OUT1. In a simple case, the result of the above operations may be viewed by correlating the value of the 4-bit input to one of the sixteen decimal tap numbers. For example, if the 4-bit digital word equals 0001 (i.e., decimal value one), then DAC 10 enables a switching transistor and a column access transistor to couple the voltage at tap T1 to V.sub.OUT1. Lastly in this regard, and assuming that each of the resistors in string 12 have the same resistance value, then the analog output voltage corresponding to the digital input will be T#/15*V.sub.REF1, where T# is the number of the tap that is accessed by the digital input signal. By way of detailed illustration of the operation of DAC 10, the example of an input equal to 0001 is now traced through DAC 10 in greater detail. From the input of 0001, its two MSBs are coupled to column decoder 14 and, thus, the value of 00 is received by column decoder 14. In response, column decoder 14 enables the gate of the column access transistor having a numeric identifier equal to the value of the MSBs. Here, the MSBs of 00 equal a decimal value of zero and, thus, column decoder 14 couples a voltage of V.sub.S1 to the gate of column access transistor CAT0. Turning now to row decoder 16, it responds to the value of the two LSBs of the 4-bit input However, note that these two LSBs pass through exclusive OR gates and, therefore, their values are unchanged when passed to row decoder 16 if the lsb equals 0, or their complements are passed to row decoder 16 if the lsb equals 1. Returning then to the example of a 4-bit input equal to 0001, the two LSBs equal 01 and the lsb of the two MSBs equals 0. Thus, the unchanged value of 01 reaches row decoder 16, and row decoder 16 in response asserts the word line having a decimal numeric identifier equal to the value of the two LSBs as received from gates EOG0 and EOG1. In the present example, therefore, row decoder 16 asserts word line WL1 high to a value of V.sub.S1 which, therefore, enables each of switching transistors ST1, ST6, ST9, and ST14. Recall also that column decoder 14 in this example enables column access transistor CAT0. As a result, the voltage from tap T1 passes via switching transistor ST1 to bit line BL0, and then passes via column access transistor CAT0 to V.sub.OUT1. Lastly, it is noted that the voltage at tap T1 is divided across one resistive element (i.e., R0) and, thus, for an input equal to 0001, the analog output voltage using voltage division is 1/15 *V.sub.REF1.
To further illustrate in detail the operation of DAC 10, consider now the example of an input equal to 0111 as traced through DAC 10. At the outset, from the general operation described above, one skilled in the art will expect that since the decimal value of 0111 equals seven, then the tap selected by DAC 10 for output is tap T7. This expectation is now confirmed through a detailed examination of this example. From the input of 0111, its two MSBs of 01 are coupled to column decoder 14. In response, column decoder 14 enables the gate of the column access transistor having a decimal numeric identifier equal to the two MSB values of 01 and, hence, the gate of column access transistor CAT1 is enabled. Turning now to row decoder 16, note first that the lsb of the two MSBs in his example equals one; consequently, gates EOG0 and EOG1 cause the complements of the two LSBs to reach row decoder 16. Thus, the complements of the 11 LSBs are 00 and, therefore, the value of 00 reaches row decoder 16. In response, row decoder 16 asserts word line WL0 high since that word line has a numeric identifier equal to the value of the two complemented LSBs. When word line WL0 is asserted, it enables each of switching transistors ST0, ST7, ST8, and ST15. Recall also that column decoder 14 in this example enables column access transistor CAT1. As a result, the voltage from tap T7 passes via switching transistor ST7 to bit line BL1, and then passes via column access transistor CAT1 to output V.sub.OUT1. Lastly, it is noted that the voltage at tap T7 is divided across seven of the fifteen resistive elements (i.e., R0 through R6) and, thus, for an input equal to 0111, the analog voltage output using voltage division is equal to 7/15 *V.sub.REF1. Accordingly, the digital input of 0111 has been converted to an analog voltage which equals this divided voltage. Given this as well as the preceding example, one skilled in the art will further appreciate that with different digital inputs, any of the switching transistors of DAC 10 may be enabled along with enabling one of the column access transistors, and for each such combination of transistors there is a corresponding output which represents a divided voltage between zero volts or any value incrementing up from zero volts by 1/15 V.sub.REF1 (assuming equal resistance among the resistive elements), and up to an output equal to V.sub.REF1.
The configuration of DAC 10 has been accepted in various contexts; however it has been observed in connection with the present embodiments that a drawback may arise in view of the difference between the string potential V.sub.REF1 and the supply voltage V.sub.S1. Particularly, assuming that access to any of the voltage taps of DAC 10 are achieved by a same polarity input, then the magnitude of V.sub.REF1 must be quite a bit smaller than V.sub.S1. This is because both column decoder 14 and row decoder 16 must be able to output a large enough voltage to allow any of the switching transistors to conduct strongly enough in its ohmic region of operation and quickly charge any capacitive load at V.sub.OUT. This requirement is perhaps best appreciated with respect to the switching transistor(s) nearest V.sub.REF1 and, thus, to further examine this concept attention is directed to switching transistor ST15. Specifically, a first source/drain of switching transistor ST15 is connected to V.sub.REF1, and its gate is connected to word line WL0 which is driven by row decoder 16. Thus, when it is desired to enable switching transistor ST15, the bias applied by word line WL0 must impose a sufficiently large gate-to-source voltage across switching transistor ST15 so that it conducts in the appropriate fashion. Due to this requirement, V.sub.REF1 cannot equal or be too near the level of V.sub.S1. In other words, if V.sub.REF1 were equal to or near V.sub.S1 and word line WL0 were asserted with this supply voltage in an effort to enable switching transistor ST15, then the gate-to-source voltage for switching transistor ST15 would be equal to or near equal to zero volts. Consequently, switching transistor ST15 would not conduct satisfactorily. As a result, it is therefore necessary as introduced above that V.sub.REF1 be sufficiently less than the supply voltage V.sub.S1. For example, with a five volt V.sub.S1, then V.sub.REF1 is typically limited to perhaps 1.0 or 2.0 volts; in other words, in a typical prior art configuration, the difference between V.sub.S1 and V.sub.REF1 is commonly on the order of 3.0 to 4.0 volts.
The preceding discussion of V.sub.REF1 relative to the DAC supply voltage V.sub.S1 has been further scrutinized by the present inventors in connection with the evolution of supply voltages in general. More specifically, while the difference between V.sub.REF1 and V.sub.S1 may not be much of a limitation for a five volt device, it is noted by the present inventors that supply voltages are now migrating downward, such as to 3.3 volts or 1.8 volts, with even lower supply voltages in the foreseeable future. While supply voltages may become US, lower, however, there is a contrary factor in the DAC art that suggests keeping V.sub.REF1 as high as possible.
Specifically, to achieve lower noise from resistive and semiconductor devices relative to the signal level, it is desirable to increase signal power; for example, increasing V.sub.REF1 correspondingly increases the signal-to-noise ratio of the DAC. Given these conflicting notions (i.e., lowering supply voltages and maintaining V.sub.REF1 as high as possible), the present inventors have recognized that there is a need to provide a DAC that operates satisfactorily with a considerably lower difference between the resistor string potential (e.g., V.sub.REF1) and the supply voltage (e.g., V.sub.S1). In addition, however, there is an additional need to provide such a DAC that may be implemented in a minimum area, such as in the case of a circuit built using a CMOS process. The present embodiments are directed to these concerns and, in providing various solutions improve both DAC and ADC technology.